A selector circuit selectively outputs one input signal from among a plurality of input signals in correspondence with a selection signal. The selector circuit is one of basic elements of a CMOS logic circuit. For example, as illustrated in a truth table in FIG. 13, a two-input selector circuit, for two input signals Q0, Q1, outputs the input signal Q0 as an output signal Z when a selection signal S1 is “0” and outputs the input signal Q1 as the output signal Z when the selection signal S1 is “1”.
As a selector circuit which realizes a function of the truth table illustrated in FIG. 13, there are ones illustrated in FIG. 14A to FIG. 14C, for example. FIG. 14A to FIG. 14C are diagrams illustrating configuration examples of a conventional two-input selector circuit.
In the selector circuit illustrated in FIG. 14A, an input signal Q1 and a selection signal S1 are inputted to a NAND (negative logical product) gate 41, and an input signal Q0 and the selection signal S1 inverted by an inverter 44 are inputted to a NAND gate 42. Outputs of the NAND gates 41, 42 are inputted to a NAND gate 43. An output of the NAND gate 43 is outputted as an output signal Z. The selector circuit illustrated in FIG. 14A outputs a value of the input signal Q0 as the output signal Z via the NAND gates 42, 43 when the selector signal S1 is “0”, and outputs a value of the input signal Q1 as the output signal Z via the NAND gates 41, 43 when the selection signal S1 is “1”.
In the selector circuit illustrated in FIG. 14B, an input signal Q1 is inputted to a transfer gate 48 composed of a P-channel MOS transistor MP21 and an N-channel MOS transistor MN21, and an input signal Q0 is inputted to a transfer gate 49 composed of a P-channel MOS transistor MP22 and an N-channel MOS transistor MN22. The two transfer gates 48, 49 are controlled to come to be in ON states (continuity states) exclusively, by a selection signal S1 and the selection signal S1 inverted by the inverter 45. In the selector circuit illustrated in FIG. 14B, the transfer gate 49 comes to be in an ON state when the selection signal S1 is “0”, a value of the input signal Q0 being outputted as an output signal Z, and the transfer gate 48 comes to be in an ON state when the selection signal S1 is “1”, a value of the input signal Q1 being outputted as the output signal Z.
The selector circuit illustrated in FIG. 14C is a selector circuit by a dynamic logic circuit. In the selector circuit illustrated in FIG. 14C, a precharge period and an evaluation period are repeated alternately and a selector function is realized in the evaluation period. An input node of an inverter 47 which outputs an output signal Z is connected to a power supply line via a 2-channel MOS transistor MP23 to a gate of which a precharge signal φpc is inputted. The input node of the inverter 47 is connected to a ground line via N-channel MOS transistors MN23, MN24 to gates of which an input signal Q1 and a selection signal S1 are inputted respectively, and connected to a ground line via N-channel MOS transistors MN25, MN26 to gates of which an input signal Q0 and the selection signal S1 inverted by an inverter 46 are inputted respectively.
In the selector circuit illustrated in FIG. 14C, in the precharge period (at this time, both the input signals Q0, Q1 are “0”) during which the precharge signal φpc is “0”, the input node of the inverter 47 is reset to be “1” and the output signal Z is reset to be “0”. In the evaluation period during which the precharge signal φpc is “1”, the input node of the precharged inverter 47 transits to “0” and the output signal Z transits to “1” when the selection signal S1 and the input signal Q1 are “1” simultaneously or when the inversion signal of the selection signal S1 and the input signal Q0 are “1” simultaneously, whereby the selector function is realized.
In the two-input selector circuits illustrated in FIG. 14A to FIG. 14C, the selector function is each realized by the inversion signal of the selection signal S1 obtained by inverting the selection signal S1 by the inverters 44, 45, 46. In contrast, as illustrated in FIG. 15A, there is suggested a two-input selector circuit which realizes a selector function by connecting P-channel MOS transistors MP31 to MP34, N-channel MOS transistors MN31 to MN34, and an inverter 51, without using an inversion signal of a selection signal S1 (see Patent Document 1).
When the selection signal S1 is “1”, the P-channel MOS transistors MP32, MP34 come to be in OFF states and the N-channel MOS transistor MN33 comes to be in an ON state, and thus a signal path of the selector circuit illustrated in FIG. 15A becomes as illustrated in FIG. 15B. When it is assumed that the N-channel MOS transistor MN31 is almost in an ON state, a circuit illustrated in FIG. 15B performs an operation of an inverter whose input is an input signal Q1, so that an output signal Z is the same value as that of the input signal Q1, which means that the input signal Q1 is selected.
When the selection signal S1 is “0”, the P-channel MOS transistor MP32 comes to be in an ON state and the N-channel MOS transistor MN33 comes to be in an OFF state, and thus the signal path of the selector circuit illustrated in FIG. 15A becomes as illustrated in FIG. 15C. When it is assumed that the P-channel MOS transistor MP34 is almost in an ON state, a circuit illustrated in FIG. 15C performs an operation of an inverter whose input is an input signal Q0, so that the output signal Z is the same value as that of the input signal Q0, which means that the input signal Q0 is selected. As described above, the selector circuit illustrated in FIG. 15A operates as a selector circuit which outputs the value of the input signal Q1 as the output signal Z when the selection signal S1 is “1”, and which outputs the value of the input signal Q0 as the output signal Z when the selection signal S1 is “0”.
[Patent Document 1] Japanese Laid-open Patent Publication No. 04-196618
As one of circuits in which a selector circuit is used, there is a decision feedback equalizer (DFE) used for a receiver of a serializer/de-serializer (SerDes). FIG. 16A is a diagram illustrating an application example of the selector circuit in the decision feedback equalizer. A selector circuit 61 selects, in correspondence with a selection signal S1, an input signal from input signals Q0, Q1 being decision results at reference voltages corresponding to cases where previous data is “0” and “1” respectively and outputs as an output signal Z. A flip-flop 62 latches the output signal Z of the selector circuit 61 in synchronization with a clock signal CK, and outputs the latched signal as an output signal OUT and outputs the latched signal to the selector circuit 61 as the selection signal S1 related to the next data.
In a decision feedback equalizer such as illustrated in FIG. 16A, an output signal of a selector circuit is feedbacked as a selection signal of the selector circuit. In a case where the decision feedback equalizer deals with a high-speed signal whose data rate or clock is of high speed, generation of the selection signal (a loop part in which the selection signal S1 is generated through the flip-flop 62 in the example of the drawing) sometimes becomes a bottleneck of a circuit operation. In this case, if an inversion signal of the selection signal is generated from the selection signal by using an inverter as in the selector circuits illustrated in FIG. 14A to FIG. 14C, there is a problem that an operating frequency of the decision feedback equalizer becomes low due to delay of the above. For example, as illustrated in FIG. 16B, as a result that an entire circuit is constituted with a differential circuit by using two selectors 61A, 61B and two flip-flops 62A, 62B, it becomes possible to generate an inversion signal of a selection signal without delay. However, if the entire circuit is constituted with the differential circuit, a circuit scale becomes twofold, and a power consumption and a circuit area also become twofold.
Though the selector circuit illustrated in FIG. 15A realizes the selector function without using the inversion signal of the selection signal S1, there is a case where a high-speed operation is not performed as described below. For example, in a case where the input signal Q1 is “0” and the input signal Q0 is “1” when the selection signal S1 is “1”, a potential of an input node N of the inverter 51 rises quickly to a potential lowered from a power supply voltage by a threshold voltage of the N-channel MOS transistor MN31. However, in order for rising to a power supply voltage level thereafter, it is necessary to wait for a leak of the N-channel MOS transistor MN31, so that a high-speed operation is not performed in a recent circuit which operates at a low voltage. Similarly, in a case where the input signal Q0 is “1” when the selection signal S1 is “0”, for example, the potential of the input node N of the inverter 51 lowers quickly to a potential raised from a ground voltage by a threshold voltage of the P-channel MOS transistor MP34. However, for lowering to a ground level thereafter, it is necessary to wait for a leak from the P-channel MOS transistor MP34, so that a high-speed operation is not be performed in a circuit operated at a low voltage.